The present invention generally pertains to phase-locked loop frequency modulation circuits and is particularly directed to frequency modulation with an input modulation signal having a low-frequency content.
A typical prior art phase-locked loop frequency modulation circuit, as shown in FIG. 1, includes a voltage controlled oscillator (VCO) 10, a frequency divider 12, a phase detector 14, a loop filter 16 and an adder 18. The VCO 10 provides an output signal 20 having a given frequency in accordance with the voltage of a control signal 22 provided to the input of the VCO 10. The frequency divider 12 divides the given frequency of the VCO output signal 20 by an integer N to provide a frequency-divided VCO output signal 24 having a frequency that is near the frequency f.sub.REF of a reference frequency signal 26. The phase detector 14 compares the phase of the frequency-divided VCO output signal 24 with the phase of the reference frequency signal 26 to provide a phase error signal 28 that is indicative of a phase difference between the reference frequency signal 26 and the VCO output signal 20. The loop filter 16 filters the phase error signal 28 to provide a loop filter output signal 30. The adder 18 adds the loop filter output signal 30 to an input modulation signal 32 having a content m(t) to provide the control signal 22 that is provided to the input of the VCO 10 to frequency modulate the output signal 20 that is provided by the VCO 10 at the given frequency. Depending upon the particular implementation, the given frequency of the VCO output signal 20 may be centered at the frequency of a broadcast transmission channel or at some intermediate frequency.
Phase-locked loop frequency modulation circuits are used in many applications, including radios for cellular broadcast systems. The content m(t) of the input modulation signal 32 is a voltage that varies in amplitude. Although a typical phase-locked loop frequency modulation circuit performs satisfactorily when the input modulation signal has its content m(t) derived from a voice signal, the transfer function of a typical phase-locked loop frequency modulation circuit is such that the typical circuit does not perform satisfactorily when the input modulation signal has its content m(t) derived from a data signal having a significant low-frequency content, i.e. a data signal having significant energy at frequencies approaching DC, which occurs for a digital data signal when there is an uneven distribution of one-bits and zero-bits . The transfer function of the typical phase-locked loop frequency modulation circuit, as shown in FIG. 1, is: EQU .DELTA..omega.(a)/m(s)=K.sub.o /[1+K.sub.o K.sub.d f(s)/s],(1)
wherein K.sub.o is the gain of the VCO, K.sub.d is the gain of the phase detector and .omega. is proportional to frequency.
This transfer function goes to zero as s goes to zero, which means that the phase-locked loop does not pass the low-frequency content of the input modulation signal, whereby for a digital data signal having an uneven distribution of one-bits and zero-bits, the bit error performance is degraded.
A solution to this problem is to provide a phase-locked loop frequency modulation circuit having a transfer function that is constant for all frequencies. This will occur if the transfer function is: EQU .DELTA..omega.(s)/m(s)=K.sub.o [1+Af(s)/s]/[1+K.sub.o K.sub.d f)s)/s], (2)
wherein A=K.sub.o K.sub.d.
Phase-locked loop frequency modulation circuits having constant transfer functions have been described in U.S. Pat. Nos. 4,052,672 to Enderby et al. and 4,242,649 to Washburn, Jr. Enderby et al. described further adding an integrated input modulation signal to the phase error signal at the input of the loop filter; and Washburn, Jr. described further adding a compensated input modulation signal to the phase error signal at the input of the loop filter, with the compensated input modulation signal being provided by processing the input modulation signal to compensate for the transfer functions of the loop components. Washburn, Jr. also alternatively described adding the compensated input modulation signal into the loop at the first node available after the input to the loop filter when an integrated circuit in which the phase-locked loop is embodied does not have an available pin at the input of the loop filter.